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| www..com W29C010 128K x 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C010 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C010 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES * Single 5-volt program and erase operations * Fast page-write operations * Low power consumption - 128 bytes per page - Page program cycle: 10 mS (max.) - Effective byte-program cycle time: 39 S - Optional software-protected data write * Fast chip-erase operation: 50 mS * Read access time: 45/70/90 nS * Typical page program/erase cycles: 1K/10K * Ten-year data retention * Software and hardware data protection - Active current: 25 mA (typ.) - Standby current: 20 A (typ.) * Automatic program timing with internal VPP generation * End of program detection - Toggle bit - Data polling * Latched address and data * TTL compatible I/O * JEDEC standard byte-wide pinouts * Available packages: 32-pin 600 mil DIP, 450 mil SOP, TSOP and PLCC -1- Publication Release Date: April 1997 Revision A1 www..com W29C010 PIN CONFIGURATIONS BLOCK DIAGRAM NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD WE NC A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS CE OE WE CONTROL OUTPUT BUFFER DQ0 . . DQ7 32-pin DIP 26 25 24 23 22 21 20 19 18 17 A0 . . A16 DECODER CORE ARRAY V/ AAA 1 1 1 N D WN 256CDEC 4 5 6 7 8 9 10 11 12 13 3 2 1 32 31 30 29 28 27 PIN DESCRIPTION A14 A13 A8 A9 A11 OE A10 CE DQ7 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 SYMBOL A0-A16 DQ0-DQ7 CE OE WE VDD GND NC PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection 32-pin PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 DD GD D DD QQNQQQQ 12D3456 -2- www..com W29C010 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C010 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29C010 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE, whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 S, after the initial byte-load cycle, the W29C010 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 S (TBLCO) from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last rising edge of WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C010 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the -3- Publication Release Date: April 1997 Revision A1 www..com W29C010 software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram. Hardware Data Protection The integrity of the data stored in the W29C010 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 3.8V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. Data Polling (DQ7)-Write Status Detection The W29C010 includes a data polling feature to indicate the end of a programming cycle. When the W29C010 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29C010 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C1h). The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. -4- www..com W29C010 TABLE OF OPERATING MODES Operating Mode Selection Operating Range = 0 to 70C (Ambient Temperature), VDD = 5V 10%, VSS = 0V, VHH = 12V MODE CE Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL OE VIL VIH X VIL X VIH VIH VIL VIL WE VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) Device Code C1 (Hex) DQ. A0 = VIL; A1-A16 = VIL; A9 = VHH A0 = VIH; A1-A16 = VIL; A9 = VHH -5- Publication Release Date: April 1997 Revision A1 www..com W29C010 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAH 55H A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 20H Sofware Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 20 to address 5555 Notes for software program code: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -6- www..com W29C010 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Sofware Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Notes for software chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -7- Publication Release Date: April 1997 Revision A1 www..com W29C010 Command Codes for Product Identification BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ALTERNATE PRODUCT (5) IDENTIFICATION ENTRY ADDRESS 5555 2AAA 5555 Pause 10 mS DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 10 mS DATA AAH 55H 80H AAH 55H 60H SOFTWARE PRODUCT IDENTIFICATION EXIT ADDRESS 5555H 2AAAH 5555H Pause 10 mS DATA AAH 55H F0H - Software Product Identification Acquisition Flow Product Identification Entry(1) Load data AA to address 5555 Product Identification Mode(2,3) Product Identification Exit(1) Load data 55 to address 2AAA Load data AA to address 5555 Load data 80 to address 5555 Read address = 0 data = DA Load data 55 to address 2AAA Load data AA to address 5555 Load data FO to address 5555 Load data 55 to address 2AAA Read address = 1 data = C1 Pause 10 mS Load data 60 to address 5555 (4) Normal Mode Pause 10 mS Notes for software product identification: (1) Data format: DQ7-DQ0 (Hex); address format: A14-A0 (Hex). (2) A1-A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. (5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- www..com W29C010 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except A9 Transient Voltage (<20 nS ) on Any Pin to Ground Potential Voltage on A9 and OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. TEST CONDITIONS MIN. LIMITS TYP. MAX. 50 UNIT Power Supply Current ICC CE = OE = VIL, WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz - mA Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS ISB1 CE = VIH, all DQs open Other inputs = VIL/VIH - 2 3 mA A A A V V V V V ISB2 ILI ILO VIL VIH VOL VOH1 VOH2 CE = VDD -0.3V, all DQs open VIN = GND to VDD VIN = GND to VDD IOL = 2.0 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.0 2.4 4.2 20 - 100 10 10 0.8 0.45 - -9- Publication Release Date: April 1997 Revision A1 www..com W29C010 Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU.READ TPU.WRITE TYPICAL 100 5 UNIT S mS CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pF pF AC CHARACTERISTICS AC Test Conditions (VDD = 5.0V 10% for 90 nS; VDD = 5.0V 5% for 45 nS and 70 nS) PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V < 5 nS 1.5V/1.5V CONDITIONS 1 TTL Gate and CL = 100 pF for 90 nS CL = 30 pF for 45/70 nS AC Test Load and Waveform +5V 1.8K D OUT 100 pF for 90 nS 30 pF for 45/70 nS (Including Jig and Scope) 1.3K Input 3V 1.5V 0V Test Point Output 1.5V Test Point - 10 - www..com W29C010 AC Characteristics, continued Read Cycle Timing Parameters (VDD = 5.0V 10% for 90 nS; VDD = 5.0V 5% for 45 nS and 70 nS, VSS = 0V, TA = 0 to 70 C) PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE High to High-Z Output OE High to High-Z Output Output Hold from Address change SYM. TRC TCE TAA TOE TCHZ TOHZ TOH W29C010-45 MIN. 45 0 MAX. 45 45 20 20 20 - W29C010-70 MIN. 70 0 MAX. 70 70 35 25 25 - W29C010-90 MIN. 90 0 MAX. 90 90 40 25 25 - UNIT nS nS nS nS nS nS nS Byte/Page-write Cycle Timing Parameters PARAMETER Write Cycle (erase and program) Address Setup Time Address Hold Time WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time SYMBOL TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC MIN. 0 50 0 0 0 0 70 70 100 50 0 TYP. MAX. 10 150 UNIT mS nS nS nS nS nS nS nS nS nS nS nS S Note: All AC timing signals observe the following guideline for determining setup and hold times: Reference level is VIH for high-level signal and VIL for low-level signal. - 11 - Publication Release Date: April 1997 Revision A1 www..com W29C010 AC Characteristics, continued DATA Polling Characteristics (1) PARAMETER Data Hold Time OE Hold Time OE to Output Delay (2) Write Recovery Time SYMBOL TDH TOEH TOE TWR MIN. 10 10 0 TYP. MAX. UNIT nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. Toggle Bit Characteristics (1) PARAMETER Data Hold Time OE Hold Time OE to Output Delay (2) OE High Pulse Write Recovery Time SYMBOL TDH TOEH TOE TOEHP TWR MIN. 10 10 150 0 TYP. MAX. UNIT nS nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A16-0 CE TCE OE TOE TOHZ VIH WE TOH DQ7-0 High-Z Data Valid TAA Data Valid T CHZ High-Z - 12 - www..com W29C010 Timing Waveforms, continued WE Controlled Write Cycle Timing Diagram TWC TAS Address A16-0 TAH CE TCS TOES TCH TOEH OE TWP TWPH WE TDS DQ7-0 Data Valid TDH Internal write starts CE Controlled Write Cycle Timing Diagram TAS Address A16-0 TAH TWC TWPH CE TOES OE WE TDS DQ7-0 High Z Data Valid TCS TCP TOEH CH T TDH Internal Write Starts - 13 - Publication Release Date: April 1997 Revision A1 www..com W29C010 Timing Waveforms, continued Page Write Cycle Timing Diagram TWC Address A16-0 DQ7-0 CE OE TWP WE Byte 0 TWPH TBLC Byte 1 Byte 2 Byte N-1 Internal Write Start Byte N DATA Polling Timing Diagram Address A16-0 WE CE TOEH OE TDH DQ7 TOE HIGH-Z TWR - 14 - www..com W29C010 Timing Waveforms, continued Toggle Bit Timing Diagram WE CE OE T OEH TDH TOE HIGH-Z TWR DQ6 Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Address A15-0 5555 2AAA 5555 Byte/page load cycle starts TWC DQ15-0 AAAA 5555 A0A0 CE OE WE TWP TWPH TBLC SW0 SW1 SW2 Word 0 Word N-1 Word N (last word) Internal write starts - 15 - Publication Release Date: April 1997 Revision A1 www..com W29C010 Timing Waveforms, continued Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode Address A15-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 20 CE OE WE TWP TWPH SW0 TBLC SW1 SW2 SW3 SW4 SW5 Internal programming starts Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A15-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 10 CE OE WE TWP TWPH SW0 TBLC SW1 SW2 SW3 SW4 SW5 Internal erasing starts - 16 - www..com W29C010 ORDERING INFORMATION PART NO. ACCESS POWER SUPPLY TIME CURRENT MAX. (nS) (mA) 45 70 90 45 70 90 45 70 90 45 70 90 45 70 90 45 70 90 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 STANDBY VDD CURRENT MAX. (A) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE CYCLING W29C010-45 W29C010-70 W29C010-90 W29C010S-45 W29C010S-70 W29C010S-90 W29C010P-45 W29C010P-70 W29C010P-90 W29C010-45B W29C010-70B W29C010-90B W29C010S-45B W29C010S-70B W29C010S-90B W29C010P-45B W29C010P-70B W29C010P-90B Notes: 600 mil DIP 600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 450 mil SOP 32-pin PLCC 32-pin PLCC 32-pin PLCC 600 mil DIP 600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 450 mil SOP 32-pin PLCC 32-pin PLCC 32-pin PLCC 1K 1K 1K 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K 10K 10K 10K 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 17 - Publication Release Date: April 1997 Revision A1 www..com W29C010 PACKAGE DIMENSIONS 32-pin P-DIP Symbol Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 0.670 0.085 14.99 13.84 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 15 17.02 2.16 5.33 D 32 17 E1 A A1 A2 B B1 c D E E1 e1 L a 1 16 eA S Notes: E c S A A2 A1 Base Plane Seating Plane L B B1 e1 a eA 1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec. 32-pin SO Wide Body 32 17 Symbol e1 Dimension in Inches Dimension in mm Min. Nom. 0.004 0.101 0.014 0.006 0.106 0.016 0.008 0.805 0.440 0.044 0.546 0.023 0.047 0.445 0.050 0.556 0.031 0.055 Max. 0.118 Min. Nom. 0.10 Max. 3.00 E HE L Detail F 1 16 b A A1 A2 b c D E e HE L LE S y Notes: c 0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004 2.57 0.36 0.15 2.69 0.41 0.20 20.45 2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10 11.18 1.12 13.87 0.58 1.19 11.30 1.27 14.12 0.79 1.40 0 10 0 10 D e1 A2 S y e A A1 LE See Detail F Seating Plane 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. - 18 - www..com W29C010 Package Dimensions, continued 32-pin PLCC H E E 4 1 32 30 Symbol 5 29 Dimension in Inches Dimension in mm Min. 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 Nom. Max. 0.140 Min. 0.50 Nom. Max. 3.56 GD D HD 13 21 14 20 c A A1 A2 b1 b c D E e GD GE HD HE L y Notes: 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0 10 0 10 L A2 A e b b1 GE A1 Seating Plane y 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. 32-pin TSOP HD Symbol Dimension in Inches Min. Nom. Max. 0.047 Dimension in mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20 D c A A1 A2 __ 0.002 0.037 0.007 0.005 0.720 0.311 0.780 __ __ 0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031 0.006 0.041 0.009 0.007 0.728 0.319 0.795 __ 0.05 0.95 0.17 0.12 18.30 7.90 19.80 __ __ 1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80 M e E b c D E HD e L L1 A A2 0.10(0.004) b __ 0.016 __ 0.024 __ 0.40 __ 0.60 __ 0.000 1 __ 0.004 5 __ 0.00 1 __ 0.10 5 Y Y __ 3 __ 3 L L1 A1 Note: Controlling dimension: Millimeters - 19 - Publication Release Date: April 1997 Revision A1 www..com W29C010 Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792647 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice & Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 20 - |
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